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CréVinn's approach to IP
Current trends in networking have expanded the role of the network interface to include complex functionality - technologies such as Secure Communications, Traffic Management and Network Storage. In parallel network line speeds have continued to increase, with Gigabit Ethernet now becoming pervasive and 10 Gigabit products already in the market. The combination of complexity and speed has driven the need to move much of this functionality into specialised processing units in the network interface. |
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Many of today's implementations are based on the use of fully programmable Network Processors, which are ideal for solving generic data handling tasks. This flexibility comes at a price - in silicon area, firmware development and scalability. For some applications, this flexibility is not required - although the complexity still often drives the use of fully - programmable network processors. The TCP protocol for example, which may require 15,000 lines of code for a standard implementation, is complex but well understood.
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CréVinn's approach is to implement such protocols using configurable Hardware State Machines. This approach allows customers to tailor cores to their particular requirements while removing the firmware development cycle, giving you the best of both worlds - minimized silicon area with the required programmability.
Our cores are developed as 'Soft Macros', making integration with our customers' target technologies a painless experience. In addition the 'soft macro' approach facilitates scaling to suit different performance requirements.
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Cores:
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| Garnet* |
Garnet is a high performance
hardware state-machine based
NAT/NAP/L2/L3 offload IP Core.
Garnet is targeted at network
gateway applications that require
high throughput NAT/NAPT
performance with supporting L3
and L2 forwarding. |
MAC-10G (OnyX)
MAC-1G
PCS: 10GBaseX (Pearl) |
Standard 10G Ethernet MAC (OnyX) with XGMII interface, and standard 1G Ethernet Mac with GMII, RGMII and TBI interfaces.
10GBaseX PCS, 64-bit XGMII-equivalent interface for lower clock speeds, interfaces to four 20-1 Serdes. |
TOE-1G(Topaz)
TOE-100M* |
TOE-1G: Gigabit TCP Offload Engine. Low gate count TOE targeted at single 1G link or multiple 100M links.
Available in 4-channel, 8 channel and 2k channel variants
TOE-100M: Minimal gate count 100Mbps TOE for low cost Internet Appliance market |
| TOE-10G* |
10 Gigabit TCP Offload Engine. Full TCP implementation incorporating Error Processing, Retransmission and RDMA support. Scalable number of connects supported, optimized to support low cost DDR SDRAM.
Supports 1X10G to 10X1G links |
Search Engine |
Contents Addressable Memory based search engine optimised for standard DDR SDRAM to provide low-cost, high density search functions for a wide variety of networking applications. |
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